The present disclosure relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit having memory macros.
In recent years, with the miniaturization in the semiconductor processes, reduction in the area of semiconductor devices and reduction in power supply voltage are in rapid progress. It is generally known that the threshold voltage Vt of transistors varies with respect to the gate width W and gate length L of the transistors by 1/√(L×W). Therefore, the finer the gate width W and gate length L of the transistors are, the larger the variations of the threshold voltage Vt of the transistors become.
In a semiconductor integrated circuit having flipflop memory cells such as a static random access memory (SRAM), it has become difficult to maintain stable characteristics of the memory cells because of variations in characteristics of transistors constituting the memory cells and reduction in power supply voltage. As a result, the yield of the semiconductor integrated circuit has decreased. In order to fabricate a semiconductor integrated circuit having stable characteristics by miniaturized processes, it is important to prevent or reduce variations in characteristics of components of the semiconductor integrated circuit.
As indicators representing characteristics of the SRAM, a static noise margin (hereinafter abbreviated as SNM) and a write level are used. The SNM represents the retention characteristic of a memory cell exhibited when a bit line pair for the memory cell is activated and the corresponding word line is activated. The larger the SNM value, the better the retention characteristic of the memory cell is. The write level represents the bit line voltage with which information in the memory cell is rewritten once the word line is activated. The larger the write level value, the better the write characteristic is.
The SNM and the write level are in the trade-off relationship. That is, when the SNM is good, write is not easy and thus the write level is low. Conversely, when the write level characteristic is good, write is easy and thus the SNM is small.
Conventionally, pull-down circuits are coupled to the word lines in the SRAM to reduce the activating voltage for the word lines, thereby reducing the conductance of access transistors of memory cells, to improve the SNM (see Japanese Patent Publication No. 2008-262637, for example).